218 search results - page 20 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
DAC
2006
ACM
14 years 3 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
CHES
2009
Springer
14 years 9 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...