218 search results - page 35 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
DAC
2007
ACM
14 years 10 months ago
2007
ACM
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
APCSAC
2004
IEEE
14 years 22 days ago
2004
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper we present an hardware implementation of the RSA algorithm for public-key cryptography. The RSA algorithm consists in the computation of modular exponentials on larg...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...