218 search results - page 40 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
HIPC
2009
Springer
13 years 5 months ago
2009
Springer
Stream computing research is moving from terascale to petascale levels. It aims to rapidly analyze data as it streams in from many sources and make decisions with high speed and a...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
DATE
1998
IEEE
14 years 9 hour ago
1998
IEEE
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...