1381 search results - page 10 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
ISCA
1997
IEEE
14 years 5 days ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
SAMOS
2004
Springer
14 years 1 months ago
2004
Springer
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitive...