1381 search results - page 48 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
DAC
1999
ACM
14 years 9 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and po...
DAC
2001
ACM
14 years 9 months ago
2001
ACM
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— With the growth of Internet users and services, the IP address has been exhausted. In order to solve this problem, the short term solution was presented, i.e., CIDR (Classless ...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...