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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 5 days ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 2 months ago
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 9 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
HPCA
2007
IEEE
14 years 8 months ago
Evaluating MapReduce for Multi-core and Multiprocessor Systems
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
Colby Ranger, Ramanan Raghuraman, Arun Penmetsa, G...
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
14 years 1 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...