134 search results - page 10 / 27 » Architecture driven circuit partitioning |
GLVLSI
2010
IEEE
14 years 27 days ago
2010
IEEE
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
DAC
1994
ACM
13 years 12 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
DAC
1998
ACM
14 years 1 days ago
1998
ACM
This paper presents a general method for computing transient sensitivities using the adjoint method in event driven simulation algorithms that employ piecewise linear device model...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
JSA
2006
13 years 7 months ago
2006
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, c...