134 search results - page 15 / 27 » Architecture driven circuit partitioning |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
We empirically assess the implications of fixed terminals for hypergraph partitioning heuristics. Our experimental testbed incorporates a leading-edge multilevel hypergraph partit...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalab...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
DAC
2004
ACM
13 years 11 months ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...