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» Architecture driven circuit partitioning
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ICCAD
2007
IEEE
144views Hardware» more  ICCAD 2007»
14 years 4 months ago
Voltage island-driven floorplanning
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
Qiang Ma, Evangeline F. Y. Young
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 4 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani
DAC
2004
ACM
14 years 8 months ago
Exploiting structure in symmetry detection for CNF
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah...
DAC
2003
ACM
14 years 1 months ago
Force directed mongrel with physical net constraints
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna P...
DAC
1996
ACM
13 years 12 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl