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VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 8 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy
DAC
1995
ACM
13 years 11 months ago
Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits
This paper presents a direct performance-driven placement algorithm for analog integrated circuits. The performance specications directly drive the layout tools without intermedi...
Koen Lampaert, Georges G. E. Gielen, Willy M. C. S...
ECRTS
2004
IEEE
13 years 11 months ago
Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems
We present an approach to partitioning and mapping for multicluster embedded systems consisting of time-triggered and eventtriggered clusters, interconnected via gateways. We have...
Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosim...
DAC
2004
ACM
14 years 8 months ago
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
This paper presents the Quantum-Dot Cellular Automata (QCA) physical design problem, in the context of the VLSI physical design problem. The problem is divided into three subprobl...
Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dy...
ISQED
2007
IEEE
123views Hardware» more  ISQED 2007»
14 years 2 months ago
General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits
In this paper, we propose a generalized block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends structure-preserving model order ...
Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fa...