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» Architectures and Design Techniques for Energy Efficient Emb...
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DAC
2002
ACM
14 years 7 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...
DAC
2005
ACM
14 years 7 months ago
Minimising buffer requirements of synchronous dataflow graphs with model checking
Signal processing and multimedia applications are often implemented on resource constrained embedded systems. It is therefore important to find implementations that use as little ...
Marc Geilen, Twan Basten, Sander Stuijk
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 7 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
14 years 4 days ago
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
DAC
2006
ACM
13 years 8 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...