643 search results - page 23 / 129 » Architectures for function evaluation on FPGAs |
ASAP
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
ICANN
2010
Springer
13 years 8 months ago
2010
Springer
Abstract. A common practice to gain invariant features in object recognition models is to aggregate multiple low-level features over a small neighborhood. However, the differences ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...
FPGA
1999
ACM
14 years 19 hour ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...