125 search results - page 14 / 25 » Area and delay trade-offs in the circuit and architecture de... |
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objec...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PL...