125 search results - page 18 / 25 » Area and delay trade-offs in the circuit and architecture de... |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus t...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...