43 search results - page 6 / 9 » Area optimization of multi-cycle operators in high-level syn... |
CASES
2008
ACM
13 years 9 months ago
2008
ACM
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
ASPDAC
2004
ACM
14 years 24 days ago
2004
ACM
—This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, t...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...