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» Assessing Instructional Technology
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ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
14 years 29 days ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
PLDI
2000
ACM
14 years 23 hour ago
Exploiting superword level parallelism with multimedia instruction sets
Increasing focus on multimedia applications has prompted the addition of multimedia extensions to most existing general purpose microprocessors. This added functionality comes pri...
Samuel Larsen, Saman P. Amarasinghe
ISQED
2008
IEEE
119views Hardware» more  ISQED 2008»
14 years 2 months ago
Instruction Scheduling for Variation-Originated Variable Latencies
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay also has variat...
Toshinori Sato, Shingo Watanabe
ICALT
2006
IEEE
14 years 1 months ago
Instruction Through The Ages: Building Pervasive Virtual Instructors for Life Long Learning
A pervasive virtual instructor is an artificially intelligent instructor that may appear transparent to the learner or appear in the form of a threedimensional graphical character...
Jayfus T. Doswell
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
13 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...