We offer a technique to partition a centralized control-flow graph to obtain distributed control in the context of asynchronous highlevel synthesis. The technique targets Huffman-...
Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Ja...
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
Luciano Lavagno, Antonio Lioy, Michael Kishinevsky
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
Abstract. As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call...
Josep Carmona, Jordi Cortadella, Victor Khomenko, ...
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...