Semiconductor design companies are in a continuous search for design tools that address the ever increasing chip design complexity coupled with strict time-to-market schedules and...
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
Logic synthesis has made impressive progress in the last decade and has pervaded digital design replacing almost universally manual techniques. A remarkable exception is computer ...
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
Mike Gordon, Juliano Iyoda, Scott Owens, Konrad Sl...