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» Automated Design of Quantum Circuits
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DAC
2009
ACM
14 years 11 months ago
The day Sherlock Holmes decided to do EDA
Semiconductor design companies are in a continuous search for design tools that address the ever increasing chip design complexity coupled with strict time-to-market schedules and...
Andreas G. Veneris, Sean Safarpour
DAC
1998
ACM
14 years 11 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
DAC
2002
ACM
14 years 11 months ago
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ti...
ASPDAC
2007
ACM
124views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands
Logic synthesis has made impressive progress in the last decade and has pervaded digital design replacing almost universally manual techniques. A remarkable exception is computer ...
Ajay K. Verma, Paolo Ienne
ENTCS
2006
176views more  ENTCS 2006»
13 years 10 months ago
Automatic Formal Synthesis of Hardware from Higher Order Logic
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
Mike Gordon, Juliano Iyoda, Scott Owens, Konrad Sl...