510 search results - page 80 / 102 » Automated Design of Quantum Circuits |
DAC
2007
ACM
14 years 11 months ago
2007
ACM
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
DAC
1998
ACM
14 years 10 months ago
1998
ACM
We describe the verification of the IM: a large, complex (12,000 gates and 1100 latches) circuit that detects and marks the boundaries between Intel architecture (IA-32) instructi...
DAC
1999
ACM
14 years 10 months ago
1999
ACM
- Closed form solutions for the 50% delay, rise time, overshoots, and settling time of signals in an RLC tree are presented. These solutions have the same accuracy characteristics ...
DAC
2001
ACM
14 years 10 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
GLVLSI
2005
IEEE
14 years 3 months ago
2005
IEEE
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...