We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
Portable systems require long battery lifetime while still delivering high performance. Dynamic voltage scaling (DVS) algorithms reduce energy consumption by changing processor sp...
Tajana Simunic, Luca Benini, Andrea Acquaviva, Pet...
Many real-time embedded systems involve a collection of independently executing event-driven code blocks, having hard real-time constraints. Tasks in many such systems, like netwo...
Samarjit Chakraborty, Thomas Erlebach, Simon K&uum...
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...