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FPL
2010
Springer
267views Hardware» more  FPL 2010»
15 years 1 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
HPCA
2003
IEEE
16 years 3 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
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ARITH
2007
IEEE
15 years 9 months ago
Optimistic Parallelization of Floating-Point Accumulation
Abstract— Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the availabl...
Nachiket Kapre, André DeHon
ACSC
2005
IEEE
15 years 9 months ago
Large Object Segmentation with Region Priority Rendering
The Address Recalculation Pipeline is a hardware architecture designed to reduce the end-to-end latency suffered by immersive Head Mounted Display virtual reality systems. A deman...
Yang-Wai Chow, Ronald Pose, Matthew Regan
VISUALIZATION
2005
IEEE
15 years 9 months ago
The Visible Radio: Process Visualization of a Software-Defined Radio
In this case study, a data-oriented approach is used to visualize a complex digital signal processing pipeline. The pipeline implements a Frequency Modulated (FM) Software-Defined...
Matthew Hall, Alex Betts, Donna Cox, David Pointer...