106 search results - page 13 / 22 » Automated Source-Level Error Localization in Hardware Design... |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...