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CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 1 months ago
Automatic synthesis of compressor trees: reevaluating large counters
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
Ajay K. Verma, Paolo Ienne
DAC
2008
ACM
14 years 8 months ago
Parameterized timing analysis with general delay models and arbitrary variation sources
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
Khaled R. Heloue, Farid N. Najm
USS
2008
13 years 9 months ago
VoteBox: A Tamper-evident, Verifiable Electronic Voting System
Commercial electronic voting systems have experienced many high-profile software, hardware, and usability failures in real elections. While it is tempting to abandon electronic vo...
Daniel Sandler, Kyle Derr, Dan S. Wallach
SIGMETRICS
2006
ACM
114views Hardware» more  SIGMETRICS 2006»
14 years 1 months ago
On suitability of Euclidean embedding of internet hosts
In this paper, we investigate the suitability of embedding Internet hosts into a Euclidean space given their pairwise distances (as measured by round-trip time). Using the classic...
Sanghwan Lee, Zhi-Li Zhang, Sambit Sahu, Debanjan ...