1151 search results - page 130 / 231 » Automatic Generation of Complex Properties for Hardware Desi... |
130
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ACSD
2005
IEEE
15 years 10 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
253
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PADL
2009
Springer
16 years 5 months ago
2009
Springer
Abstract. In this paper, we present our initial design and implementation of a declarative network verifier (DNV). DNV utilizes theorem proving, a well established verification tec...
180
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EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
The paper presents an approach for performance and complexity analysis of hardware/software implementations for real-time systems on every stage of the partitioning. There are two...
148
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ICCAD
1998
IEEE
15 years 8 months ago
1998
IEEE
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
112
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DAC
2008
ACM
16 years 5 months ago
2008
ACM
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...