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ISLPED
2007
ACM
109views Hardware» more  ISLPED 2007»
13 years 9 months ago
A multi-model power estimation engine for accuracy optimization
RTL power macromodeling is a mature research topic with a variety of equation and table-based approaches. Despite its maturity, macromodeling is not yet widely accepted as an indu...
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Rober...
OSDI
2002
ACM
14 years 8 months ago
Using Model Checking to Debug Device Firmware
Device firmware is a piece of concurrent software that achieves high performance at the cost of software complexity. They contain subtle race conditions that make them difficult t...
Sanjeev Kumar, Kai Li
ECBS
2009
IEEE
164views Hardware» more  ECBS 2009»
14 years 2 months ago
Semantically Enhanced Containers for Concurrent Real-Time Systems
Future space missions, such as Mars Science Laboratory, are built upon computing platforms providing a high degree of autonomy and diverse functionality. The increased sophisticat...
Damian Dechev, Peter Pirkelbauer, Nicolas Rouquett...
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 4 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...