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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 9 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
DATE
2003
IEEE
114views Hardware» more  DATE 2003»
15 years 9 months ago
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering
This paper presents a new technique for automatically creating analog circuit models. The method extracts - from trained neural networks - piecewise linear models expressing the l...
Simona Doboli, Gaurav Gothoskar, Alex Doboli
TASE
2009
IEEE
15 years 10 months ago
Fault-Based Test Case Generation for Component Connectors
The complex interactions appearing in service-oriented computing make coordination a key concern in serviceoriented systems. In this paper, we present a fault-based method to gene...
Bernhard K. Aichernig, Farhad Arbab, Lacramioara A...
140
Voted
SIGCOMM
2006
ACM
15 years 10 months ago
Systematic topology analysis and generation using degree correlations
Researchers have proposed a variety of metrics to measure important graph properties, for instance, in social, biological, and computer networks. Values for a particular graph met...
Priya Mahadevan, Dmitri V. Krioukov, Kevin R. Fall...
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 9 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...