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ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
14 years 4 months ago
Improved ZDN-arithmetic for Fast Modulo Multiplication
In 1987 Sedlak proposed a modulo multiplication algorithm which is suitable for smart card implementation due to it’s low latency time. It is based on ZDN (zwei_drittel_N) arith...
Hagen Ploog, Sebastian Flügel, Dirk Timmerman...
RTAS
2005
IEEE
14 years 20 days ago
Energy-Aware Task Allocation for Rate Monotonic Scheduling
We consider the problem of energy minimization for periodic preemptive hard real-time tasks that are scheduled on an identical multiprocessor platform with dynamic voltage scaling...
Tarek A. AlEnawy, Hakan Aydin
ANCS
2008
ACM
13 years 9 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
ISLPED
2005
ACM
109views Hardware» more  ISLPED 2005»
14 years 20 days ago
Power reduction by varying sampling rate
The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a ...
William R. Dieter, Srabosti Datta, Wong Key Kai
ICCD
2008
IEEE
157views Hardware» more  ICCD 2008»
14 years 4 months ago
Power-aware soft error hardening via selective voltage scaling
—Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking...
Kai-Chiang Wu, Diana Marculescu