This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
Nicola Campregher, Peter Y. K. Cheung, Milan Vasil...
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affect...
Charles E. Stroud, Sajitha Wijesuriya, Carter Hami...
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...