233 search results - page 15 / 47 » Balance Testing of Logic Circuits |
CHES
2005
Springer
14 years 1 months ago
2005
Springer
During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on imple...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
EVOW
2001
Springer
13 years 12 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of cl...