233 search results - page 20 / 47 » Balance Testing of Logic Circuits |
GLVLSI
2003
IEEE
14 years 24 days ago
2003
IEEE
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
DFT
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detec...