233 search results - page 21 / 47 » Balance Testing of Logic Circuits |
ATS
2000
IEEE
13 years 12 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
JCIT
2008
13 years 7 months ago
2008
The main objective of design methodology of a controller for forecasting cardiac arrest using fuzzy logic approach is to provide the prediction of period of life time for the pati...