233 search results - page 25 / 47 » Balance Testing of Logic Circuits |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
DFT
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
DAC
2004
ACM
14 years 29 days ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...