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» Balance Testing of Logic Circuits
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FPGA
2004
ACM
120views FPGA» more  FPGA 2004»
14 years 29 days ago
Flexibility measurement of domain-specific reconfigurable hardware
Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
Katherine Compton, Scott Hauck
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
14 years 2 months ago
Automated Testability Enhancements for Logic Brick Libraries
Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT ...
Jason G. Brown, Brian Taylor, Ronald D. Blanton, L...
ISLPED
2005
ACM
91views Hardware» more  ISLPED 2005»
14 years 1 months ago
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 4 months ago
Reduction of Crosstalk Pessimism using Tendency Graph Approach
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred ...
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
14 years 1 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram