233 search results - page 42 / 47 » Balance Testing of Logic Circuits |
DAC
2001
ACM
14 years 9 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
FPGA
2005
ACM
14 years 2 months ago
2005
ACM
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
FPGA
2005
ACM
14 years 2 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
ISMVL
2000
IEEE
14 years 29 days ago
2000
IEEE
We have developed two novel methods of fabricating very small Si single-electron transistors (SETs), called PAtternDependent OXidation (PADOX) and Vertical PAttern-Dependent OXida...