117 search results - page 12 / 24 » Balancing power consumption in multiprocessor systems |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-onChip (MPSoC) architectures. In an earlier paper we proposed a energ...
NANONET
2009
Springer
14 years 5 days ago
2009
Springer
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating “hot spot...
3DIC
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...