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DAC
1998
ACM
14 years 8 months ago
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
Yehia Massoud, Steve S. Majors, Tareq Bustami, Jac...
ICCAD
2005
IEEE
95views Hardware» more  ICCAD 2005»
14 years 4 months ago
TACO: temperature aware clock-tree optimization
— In this paper, an efficient linear time algorithm TACO is proposed for the first time to minimize the worst case clock skew in the presence of on-chip thermal variation. TACO...
Minsik Cho, Suhail Ahmed, David Z. Pan
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
14 years 1 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
AISADM
2005
Springer
14 years 29 days ago
Execution Engine of Meta-learning System for KDD in Multi-agent Environment
Meta-learning system for KDD is an open and evolving platform for efficient testing and intelligent recommendation of data mining process. Metalearning is adopted to automate the s...
Ping Luo, Qing He, Rui Huang, Fen Lin, Zhongzhi Sh...
HPCC
2005
Springer
14 years 28 days ago
High Performance Subgraph Mining in Molecular Compounds
Structured data represented in the form of graphs arises in several fields of the science and the growing amount of available data makes distributed graph mining techniques partic...
Giuseppe Di Fatta, Michael R. Berthold