436 search results - page 52 / 88 » Benchmarking and hardware implementation of JPEG-LS |
ISSS
2002
IEEE
14 years 19 days ago
2002
IEEE
Application specific systems have potential for customization of design with a view to achieve a better costperformance-power trade-off. Such customization requires extensive de...
MICRO
2002
IEEE
14 years 19 days ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
ATS
2000
IEEE
14 years 4 days ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
ISLPED
1999
ACM
14 years 1 days ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
MICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...