686 search results - page 29 / 138 » Benchmarking cerebellar control |
RTAS
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper presents a novel approach for calculating a probabilistic worst-case response-time for messages in the Controller Area Network (CAN). CAN uses a bit-stuffing mechanism...
MICRO
2002
IEEE
14 years 2 months ago
2002
IEEE
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
ICCD
2002
IEEE
2002
IEEE
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
14 years 6 months ago
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...