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VLSID
1993
IEEE
234views VLSI» more  VLSID 1993»
13 years 11 months ago
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V....
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 11 months ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
DAC
2006
ACM
14 years 8 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
DAC
2009
ACM
14 years 8 months ago
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic t...
Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang
FPGA
1997
ACM
142views FPGA» more  FPGA 1997»
13 years 11 months ago
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current a...
Jonathan Rose, Dwight D. Hill