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DELTA
2008
IEEE
14 years 3 months ago
Improved Policies for Drowsy Caches in Embedded Processors
In the design of embedded systems, especially batterypowered systems, it is important to reduce energy consumption. Cache are now used not only in general-purpose processors but a...
Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroak...
LCTRTS
2010
Springer
14 years 1 months ago
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, cac...
Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
14 years 10 days ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ASPLOS
2006
ACM
14 years 2 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
DATE
2004
IEEE
132views Hardware» more  DATE 2004»
14 years 10 days ago
LZW-Based Code Compression for VLIW Embedded Systems
We propose a new variable-sized-block method for VLIW code compression. Code compression traditionally works on fixed-sized blocks and its efficiency is limited by the small block...
Chang Hong Lin, Yuan Xie, Wayne Wolf