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» Bounded-lifetime integrated circuits
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DAC
2009
ACM
16 years 5 months ago
Thermal-driven analog placement considering device matching
With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the ther...
Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-...
DAC
1999
ACM
16 years 5 months ago
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, ...
DAC
2004
ACM
16 years 5 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
DAC
2006
ACM
16 years 5 months ago
Power-centric design of high-speed I/Os
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojan...
DAC
2006
ACM
16 years 5 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....