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TIM
2010
294views Education» more  TIM 2010»
13 years 1 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
DAC
2007
ACM
13 years 10 months ago
CAD Implications of New Interconnect Technologies
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a repl...
Louis Scheffer
DAC
1994
ACM
13 years 10 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik
TVLSI
1998
135views more  TVLSI 1998»
13 years 6 months ago
Wave-pipelining: a tutorial and research survey
— Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of hig...
Wayne P. Burleson, Maciej J. Ciesielski, Fabian Kl...
NIPS
1992
13 years 8 months ago
Silicon Auditory Processors as Computer Peripherals
Several research groups are implementing analog integrated circuit models of biological auditory processing. The outputs of these circuit models have taken several forms, includin...
John Lazzaro, John Wawrzynek, Misha Mahowald, Mass...