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ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 11 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey
ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
13 years 11 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
DAC
2009
ACM
14 years 8 months ago
ILP-based pin-count aware design methodology for microfluidic biochips
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
Cliff Chiung-Yu Lin, Yao-Wen Chang
DAC
2002
ACM
14 years 8 months ago
ILP-based engineering change
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng...
DAC
2006
ACM
14 years 8 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin