137 search results - page 25 / 28 » Branch Misprediction Prediction: Complementary Branch Predic... |
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
Redundant threading architectures duplicate all instructions to detect and possibly recover from transient faults. Several lighter weight Partial Redundant Threading (PRT) archite...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
ICS
1998
Tsinghua U.
13 years 11 months ago
1998
Tsinghua U.
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
ISLPED
2003
ACM
14 years 22 days ago
2003
ACM
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...