21 search results - page 3 / 5 » Buffer Insertion Considering Process Variation |
ICCAD
2003
IEEE
14 years 21 days ago
2003
IEEE
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flo...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
AUTOMATICA
2008
13 years 7 months ago
2008
This paper studies a general dynamic buffer management problem with one buffer inserted between two interacting components. The component to be controlled is assumed to have multi...