69 search results - page 4 / 14 » Buffer insertion for clock delay and skew minimization |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...