69 search results - page 6 / 14 » Buffer insertion for clock delay and skew minimization |
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
CSREAESA
2004
13 years 10 months ago
2004
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the device...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...