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» Buffered Crossbar Fabrics Based on Networks on Chip
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HPCA
2003
IEEE
14 years 8 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
DAC
2009
ACM
14 years 8 months ago
Interconnection fabric design for tracing signals in post-silicon validation
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to ...
Xiao Liu, Qiang Xu
MICRO
2006
IEEE
98views Hardware» more  MICRO 2006»
14 years 1 months ago
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
Chrysostomos Nicopoulos, Dongkook Park, Jongman Ki...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 8 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
14 years 2 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...