This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...