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» Built-in test generation for synchronous sequential circuits
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ICES
2000
Springer
140views Hardware» more  ICES 2000»
15 years 8 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 8 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
15 years 11 months ago
Optimal High-Resolution Spectral Analyzer
This paper presents a new application field for the Goertzel algorithm. The test of mixed-signal circuits involves the generation and analysis of signals. A standard method for th...
A. Tchegho, Heinz Mattes, Sebastian Sattler
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
15 years 8 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
15 years 8 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...